The present invention relates to a semiconductor chip, and more specifically to a semiconductor chip mountable over a desired one of two packages with mutually different numbers of terminals.
Conventionally, there is a semiconductor chip mountable over a desired one of a first package having N-number (N is a natural number) of terminals and a second package having M-number (M is an integer larger than N) of terminals. This semiconductor chip is provided with: a dedicated pad for setting the number of terminals of the package mounted with the semiconductor chip; and M-number of pads.
In a case where the semiconductor chip is mounted over the first package, the dedicated pad and a power supply pad receiving supply voltage are coupled to each other by a bonding wire. Moreover, N-number of pads of the M-number of pads of the semiconductor chip are respectively coupled to N-number of terminals of the first package by N-number of bonding wires. An internal circuit of the semiconductor chip operates as a first semiconductor device having N-number of terminals in response to provision of the supply voltage to the dedicated pad.
Moreover, in a case where the semiconductor chip is mounted over the second package, the dedicated pad and a grounding pad receiving grounding voltage are coupled to each other by a bonding wire. Moreover, the M-number of pads of the semiconductor chip are respectively coupled to M-number of terminals of the second package by M-number of bonding wires. The internal circuit of the semiconductor chip operates as a second semiconductor device having the M-number of terminals in response to provision of the grounding voltage to the dedicated pad.
Japanese Unexamined Patent Publication No. 2002-198491 discloses a technology of dividing a pad into a plurality of electrodes for reducing adverse effect exerted on a transistor by plasma via the pad in semiconductor chip manufacturing processes.